The Inventors have contrived a new method, which can be called a “facet growth method”, for producing thick, low-dislocation GaN crystal substrates. A substrate is a basic board on which devices are fabricated. A substrate is sometimes called a “wafer”. The facet growth method has a history of improvements which have been done by the Inventors of the present invention. There have been three preceding facet growth methods. All the three preceding facet growth methods are explained.
{circle around (1)} Japanese Patent Laying Open No. 2001-102307 (Japanese patent application No. 11-273882) proposes a method of growing GaN crystals by making many facets and facet pits on a surface of the growing crystal on purpose, not burying the pits and maintaining the facets till the end of GaN crystal growth. FIG. 22 denotes an undersubstrate S for the facet growth. The undersubstrate has no mask. Vapor phase growth inherently produces facets Φ and facet pits. Conventional vapor phase growth methods had tried to eliminate the facets and to make a flat C-plane on the top by controlling conditions of growth. On the contrary, the facet growth method does not bury the facet pits but maintains the facets and facet pits. The facet growth method contradicts the conventional methods, which may be called a “C-plane growth” method. Facets Φ denote crystallographic planes having low Miller indices (khmn). Low Miller indices mean indices k, h, m and n are 0, ±1, ±2 or so. A set of facets form a pit of facets.
FIG. 23 shows a GaN film having facet pits on a surface which is made by the facet growth method. A facet pit is an assembly composed of six facets or twelve facets. Six or twelve facets make inverse hexagonal cones or inverse dodecagonal cones. Plenty of facet pits having a variety of shapes and sizes are randomly dispersed on the GaN surface. The GaN crystal grows upward in the direction of the c-axis as a whole. The average direction of growth is the c-axis direction. But in the facet pits, crystals grow in inner slanting directions normal to the facets. Dislocations on the facets extend in the inner slanting directions normal to the facets, and come up to and assemble to boundaries of the facets. The dislocations further come up to the bottom of the pits. Many dislocations converge to the bottom of the pits and form a linear defect hanging from the bottom of the facet pit. Dislocations are continual strings which are not easily vanished. Dislocations lying on the facets are pulled to the bottom of the facet pits. Then dislocations in other parts except the pit bottom are reduced. Low dislocation density regions are produced below the facets. The facet growth method intentionally produces random facets by controlling the conditions of growth. The facet pits attract, absorb and arrest dislocations at the pit bottoms. A variety of sizes of pits are dispersed at a variety of positions on the C-plane surface at random. The first method is called a “random facet growth” method.
The random facet growth method has drawbacks. The GaN crystal prepared by the method, which has defects (dislocations) dispersing on surfaces at random, is not preferable to make devices thereon. Plenty of dislocations, which are gathered but not arrested at the pit bottoms, are released again from the bottom with the progress of growth. Such drawbacks degrade the random facet growth method.
{circle around (2)} Japanese Patent Laying Open No. 2003-165799 (Japanese Patent Application No. 2002-230925) proposed a GaN vapor phase growing method of spotting an undersubstrate with isolated round dot masks for predetermining the positions of facet pits with accuracy. FIG. 24 denotes an undersubstrate S provided with dispersed isolated small dot masks S. The area S1 of covered parts  is far narrower than the area S2 of exposed part Π (S1<S2). The relation is inverse to the ELO method. S1<S2 is always valid in facet growth methods. The facet growth method differs from the ELO in the relation. A mask pitch (˜100 μm) of the facet growth method is far longer than the window pitch (˜1 μm) of the ELO method. Crystals begin to grow on the exposed part Π. The crystals growing on the exposed parts Π couple together and form a flat C-plane as a top surface. The mask has a function of impeding and delaying crystal growth. A start of growing on the masks is retarded. Delay of the crystal growth on the masks M makes facet pits having bottoms coinciding with the isolated masked parts . Facets are crystallographical planes slanting to the C-plane. The facet growth method does not bury facet pits and maintains the facet pits till the end of the growth.
The facets grow in directions of normals of the facets. Dislocations extend in parallel to the growing directions. Slanting growth of a facet sweeps dislocations D lying on the facet to boundaries of facets. The facet slanting growth lowers the dislocations along the boundaries and assembles the dislocations to the pit bottom. High density of dislocations are gathered at the parts just above the masks M. All dislocations are swept away from the facets, are lifted down and are gathered to the pit bottoms above the masks M by the facet growth. In reality dislocations do not lower or lift down but rise upward. Since the standpoint of observation is rising at the speed of the C-plane growth, the dislocations in the facet pits seem to go down. The parts above the masks M (covered parts ) become defect accumulating regions H. Since the defect accumulating regions H attract, absorb, arrest and accommodate plenty of dislocations, neighboring parts below the facets on the exposed parts become low dislocation density. The regions are called “low defect density single crystal regions Z”.
A crystal out of the pits maintains a flat C-plane top surface and grows upward on the expose part Π. Since dislocations in the part are deprived of the facets, the crystals are also low dislocation density and single crystals. The part is called a “C-plane growth region Y”. The facet-grown crystal has a concentric structure of “HZY”. FIG. 25 demonstrates a facet-growing crystal on an undersubstrate S. Y has a continual plateau of the C-plane top. Z has facets Φ. H is a facet pit bottom concealed by Y in the Figure. Since the facets are maintained throughout the growth, the final crystal ingot made by the facet growth method has a rugged surface with many concavities. The GaN ingot is sliced in a plane parallel to the C-plane. As-cut GaN wafers are obtained. Both surfaces are polished. Mirror wafers are prepared. A GaN mirror wafer is transparent like a glass plate. FIG. 26 shows a plan view of a GaN mirror wafer which has the concentric “HZY” structure. Cathode luminescence observation discriminates Y, Z and H. Y, A and H are regions piercing from the top to the bottom of the wafer. The positions of H coincide with the positions of the masks Y. The regions Z coincide with the facets. The region Y coincides with the C-plane top in FIG. 25. Z and Y are formed on the exposed part Π. This is called a dot-type facet growth method, since isolated small dot masks are dispersed for making isolated facet pits.
The dot-type facet growth method produces conical facet pits above the dot masks. Dislocations are absorbed and arrested at the bottoms of the pits. An assembly of dislocations forms a defect accumulating region H at the pit bottom above the mask. Once arrested dislocations are not released from the defect accumulating regions H formed above the masks. An advantage is the occurrence of the low defect density single crystal regions Z below the facets on the exposed part.
The dot-type facet growth method disperses isolated dot masks on the undersubstrate and allows the dot masks to make concentric facet pits. A wide extra space, which corresponds to Y, is left untouched out of the facet pits. The function of the facets of reducing dislocations is insufficient in the C-plane growth region Y. The C-plane growth region (Y) has still many dislocations. The C-plane region Y has high electric resistance. The dot-facet growth is not favorable for making high conductive n-type GaN substrates.
Anther problem is that existence of the defect accumulating regions H prevents device makers from making a plurality of equivalent devices on the same conditions. The random-type facet growth method and the dot-type facet growth method had been invented by the same Inventors as the present invention.
{circle around (3)} Japanese Patent Laying Open No. 2003-183100 (Japanese Patent Applications No. 2002-269387) has proposed another facet growth method of covering an undersubstrate with a mask having a plurality of parallel straight covering stripes, growing gallium nitride on the stripe masked undersubstrate, forming parallel straight-extending facetted hills on parallel exposed parts Π, forming parallel straight-extending valleys on the covered stripe parts , pulling dislocations on the facets of the hills to the valleys and attracting/accumulating/arresting the dislocations in regions H formed at the bottoms of the valleys above the stripe covered parts . FIG. 27 demonstrates an undersubstrate S provided with parallel straight mask stripes M. The numbers of covered parts  and the exposed parts are same. But the area S1 of the covered parts  is far narrower than the area S2 of the exposed parts Π (S1<<S2). There are several tens of stripes  and several tens of exposed parts Π on an undersubstrate, although only two stripes are depicted. The masks have a function of prohibiting crystal growth. Vapor phase crystal growth starts on the wide exposed parts Π. Parallel crystal hills with side facets are formed on the exposed parts Π. After the formation of the facet hills on the exposed parts Π, crystal growth starts on the covered parts . Differences of starting times and growing speeds make parallel facet hills on the exposed parts Π and V-grooves on the stripe covered parts  of GaN crystals.
Since masks are parallel stripes, an assembly of facets does not form polygonal pits but makes a parallel extending hill/valley structure. FIG. 28 demonstrates the hill/valley structure of a growing crystal. The bottoms of the V-valleys coincide with the covered (masked) parts . Reciprocal slanting walls appear on the exposed parts Π. The two slanting walls are facets Φ. The hill or V-groove has only two facets. The hill/valley structure is different from the dot-type facet pit having six or twelve facets in the point.
The facet growth method does not bury the V-grooves but keeps the hill/valley structure. Since crystals grow in the directions normal to the facets, dislocations extend in slanting directions normal to the facets. Dislocations existing on the facets slide from the facets, fall in the valleys and converge at the bottoms of the valleys. Dislocations lying on the facets are attracted and arrested to the bottoms. The valley bottoms become defect accumulating regions H. Crystals growing below the facets become low dislocation density single crystals. The bottom defect accumulating region H is sandwiched by low dislocation single crystal regions Z and Z. The C-plane growth region Y lies aside of Zs. A parallel-extending periodic structure of . . . HZYZHZY . . . is produced in the facet-growing GaN crystal. This facet growth method has an advantage of making low dislocation density single crystal regions Z in a shape of linearly extending stripes. The linearly extending Z is favorable for making devices on the GaN substrate. FIG. 28 demonstrates a facet-growing GaN crystal having valley bottom defect accumulating regions H, low dislocation single crystal regions Z covered with inclining facets, and C-plane growth tops.
The stripe facet method can eliminate C-plane regions Y by narrowing a mask pitch p and composing V-hill/valleys only of facets. Narrow mask pitches p (p<800 μm) less than 800 μm have the possibility of extinguishing C-plane regions. Wider mask pitches p ranging from more than 800 μm to 2000 μm (800μ<p<2000 μm) still give facets the effect of decreasing dislocations. Farther wider mask pitches p than 2000 μm (p>2000 μm) foreclose facets from the function of dislocation reduction.
The stripe mask pitch described in {circle around (3)} Japanese Patent Laying Open No. 2003-183100 should be less than 2 mm (p<2000 μm). Another drawback is a tendency of break and split of wafers because of the parallel stripes of Hs, Zs and Ys. This is named “stripe facet growth” method, since H, Z and Y are all parallel stripes.
Three preceding facet growth methods contrived by the present invention have been clarified. The random facet growth method proposed by {circle around (1)} Japanese Patent Laying Open No. 2001-102307 makes random distribution of pits without mask S (S1=0). The dot facet growth method proposed by {circle around (2)} Japanese Patent Laying Open No. 2003-165799 makes regularly distributing isolated dots of Hs and circular Zs concentrically around the isolated Hs by using dot masks (S1<S2). The stripe facet growth method proposed by ({circle around (3)} Japanese Patent Laying Open No. 2003-183100 makes a parallel structure of HZYZHZYZH . . . by using parallel stripe masks (S1<S2).
The stripe facet growth method proposed by {circle around (3)} Japanese Patent Laying Open No. 2003-183100 is useful for making low dislocation density GaN substrate crystals. However, there are still some problems to be solved.
Problem (1): The stripe facet growth method arranges parallel, linear defect accumulating regions H in a GaN crystal substrate. Facets Φ are parallel to the linear Hs. No facet is made in vertical sides to Hs, so that the dislocation reduction is insufficient. Dislocations are bent to directions vertical to the growing plane. Dislocation decrement does not occur at the spots which are free from facets. The dot facet growth method proposed by {circle around (2)} Japanese Patent Laying Open No. 2003-165799 forms many conical facet pits which have a variety of kinds of facets Φ. Strong forces originating from the conical facets gather dislocations into facet pits. On the contrary, the stripe facet growth method proposed by {circle around (3)} Japanese Patent Laying Open No. 2003-183100 gives two kinds facets a weak power of gathering dislocations to the valley bottoms, so that the dislocation reduction is unsatisfactory.
Problem (2): Chip-separation requires mechanical dicing. Mechanical dicing sometimes gives damage to device chips by introducing defects, e.g., fine granules of diamond or SiC, to sections and causing multiplications of defects. The damage degrades the device.
Problem (3): When light emanates from a three-dimensional emission box, wider superficial area per unit volume strengthens light emission. Triangle chips are more advantageous than square chips in some cases. In other cases, hexagon chips are more effective than square chips. In the case of LEDs, the more the number of surfaces increases, the more the amount of light to emanate increases. It is possible to make non-square chip LEDs on GaN wafers. It is, however, difficult to mechanically cut the processed GaN wafer into non-square LED chips.
Problem (4): Mechanical dicing, which cuts an object with a sharp blade along a straight line, can easily prepare a plurality of square chips by cutting a processed wafer lengthwise and crosswise. To cut triangle chips or hexagonal chips are difficult for mechanical dicing, because the cutting locus must change for cutting triangles or hexagons. If triangles or hexagons were cut by mechanical dicing, plenty of segment wastes would accompany. If chip-separation were done by non-mechanical means, non-square device chips would be produced without wastes.
Problem (5): {circle around (3)} Japanese Patent Laying Open No. 2003-183100 alleges that the sum of the widths of two low defect density single crystal regions Z and the width of a C-plane growth region Y should be less than 2 mm (10 μm to 2000 μm). The width of a good single crystal part is less than 2 mm. The stripe facet grown GaN substrate is inapplicable to a big device which requires a large low defect density zone wider than 2 mm. The stripe facet grown substrate with an under 2 mm good zones is incapable of making large-sized devices, for example, high luminosity LEDs or high power FETs.